1. Field of the Invention
The present invention relates to the field of semiconductor fabrication and, more particularly, to a method for removing post-etch residues in a trench/via opening, which is etched into low-k dielectric films with at least one metal layer as a hard mask.
2. Description of the Prior Art
As pitches between interconnection wirings of integrated circuits shrink to very deep sub-micron scale or beyond, post-etch trench/via residual looms as a major issue regarding the success in damascene or dual damascene processes. Several prior arts have addressed this problem.
For example, U.S. Pat. No. 6,797,627 filed Dec. 5, 2001 to Shih et al. discloses a dry-wet-dry solvent-free process for removing polymer residuals, which are allegedly mixed with copper oxide substances, from the damascened trench/via bottom and sidewalls. The proposed method is carried out after the nitride or carbide cap layer exposed by the via opening is removed. This invention limits itself to C—F based and Cu—F based polymers that are formed as part of the process of removing the cap layer from the bottom surface of an opening that has been created through one or more layers of low-k dielectrics.
According to U.S. Pat. No. 6,797,627, as set forth in the claims thereto, the proposed method must start with an O2—, N2—, or H2-based plasma treatment that interacts with polymer residuals and must create water-soluble byproducts. A de-ionized water rinse follows to remove the water-soluble byproducts and polymer from the sidewalls of the via opening. A reducing H2-based plasma treatment is then carried out to reduce copper oxide and to remove the polymer from the bottom of the via opening.
U.S. Pat. No. 6,465,352 filed Jun. 12, 2000 to Aoki discloses a dry-wet process for removing the resist film and dry-etching residue in a semiconductor device fabrication process. The proposed method starts with a H2/N2 plasma treatment, followed by an amine-based wet treatment. According to this patent, the H2/N2 plasma treatment changes the properties of a so-called resist surface hardened layer such that it can be removed later, along with the etching residue, by the succeeding amine-based wet treatment.
However, the results presented by the aforesaid prior art methods have been proven to be not satisfactory, particularly in some circumstances when a metal hard mask is applied during the etching of a trench/via hole in the dual damascene processes. The state-of-the-art metal hard mask technology may be found in, for example, U.S. Pat. No. 6,638,871 filed Jan. 10, 2002 to Wang et al., which is assigned to the same party as that of the present application, and which discloses a damascene process involving the use of a stacked dielectric-metal-dielectric hard mask.
It is believed that the composition of the trench/via residuals, which are produced when the trench/via hole is etched into low-k dielectric films with a metal layer such as titanium or titanium nitride as a hard mask, has become much more complex than ever. Therefore, it is difficult to remove such trench/via residuals by using traditional approaches.
Hitherto, the newly formulated polymer residuals arose due to the use of a metal hard mask and the solution to effectively remove such polymer residuals are not yet addressed by any of the prior arts. Hence, there is a need in this industry to provide an improved method for eliminating such newly formulated polymer residuals without adversely affecting the performance of the integrated circuit.